Increasingly, individual chips of a deployed information system include wireless communication ability. WCAN or wireless chip area networks may provide for the communication of various chips within a system without direct wiring.
Wireless inter-chip communication systems using pulse injection-locking for receiver phase synchronization achieve a data rate of 500 Mbps (megabits per second), but exhibit severe multipath interference within a device chassis thereby severely degrading the receiver bit error rate BER at high data-rates due to the inter-symbol interference. There are several solutions of this problem:                Make the pulse repetition period longer than the length of the channel response. However, this significantly reduces the transmission speed to 125 Mbps.        Use transmitter side equalizer (precoder) to reduce only the 2-3 most severe multipath reflections. This complicates the circuit of the transmitter.        Use an equalizer at the receiver. This also significantly complicates the receiver circuit.        
All of these proposed solutions have significant disadvantages, either resulting in non-optimal transmission speed or a significantly more complicated circuit.
Therefore, a solution is needed to optimize transmission speed.